1. Field of the Invention
The present invention relates to an 8/9 coding apparatus used in a digital data recorder.
2. Description of the Related Art
One format for digital data recorders is the ID-1 system described in "ANSI X3.17-1990".
In the recording system of such a digital data recorder, the recording data is subjected to two types of error correction coding by an outer code and an inner code, randomization, 8/9 coding, NRZI(1) modulation, magnetization, and optimization of recording, then is recorded on a recording medium.
Here, the 8/9 coding is for converting a randomized serial byte stream to a 9-bit NRZL word stream. By this conversion, after the next performed NRZI(1) modulation of the 9-bit NRZL word stream, it becomes possible to obtain a recording wave form in which the DC component is suppressed.
Below, an explanation will be made of an 8/9 coding apparatus not covered by this application.
FIG. 1 is a view of the configuration of an 8/9 coding apparatus not covered by this application. The 8/9 coding apparatus 1 has a data table 2, a polarity table 3, a codeword digital sum (CDS) table 4, a polarity register 5, a converter 6, a digital sum variation (DSV) adder 7, and a table selector 8.
The data table 2 is a table for converting the randomized serial byte stream to a 9-bit NRZL word stream and has a data table (+) 2a and a data table (-) 2b which are selectively used by the switching of the selector 2c according to the conditions at the time of the conversion.
The polarity table 3 defines the rules indicating whether or not the signal will be inverted after the 8/9 coding and has a polarity table (+) 3a and a polarity table (-) 3b which are selectively used by the switching of the selector 3c according to the conditions at the time of the conversion.
The CDS table 4 is a table storing the CDS value of the data after the 8/9 coding and has a CDS table (+) 4a and a CDS table (-) 4b which are selectively used by the switching of the selector 4c according to the conditions at the time of the conversion.
Here, the CDS shows the cumulative value of the bits from the head to the tail of the wave form of one NRZI(1) symbol. The cumulative addition is carried out by defining the code "1" of the NRZI(1) as "+1" and defining "0" as "-1".
The DSV is the cumulative value of the values of the recording wave form of the NRZI(1) for all 9-bit symbols contained in one sector. Accordingly, DSV becomes a value obtained by cumulatively adding all 9-bit symbol CDSs contained in one sector.
The polarity register 5 is a register holding the polarity of the current signal and records the polarity inversion data from the polarity table 3.
The converter 6 converts the input signal from NRZL to NRZI.
The DSV adder 7 calculates the DSV value for a period from the head of the sector to the present time as shown in the following Table 1 by using a sector start indication signal S10, the CDS data S4, and the polarity inversion data S5 and holds the result of the calculation.
TABLE 1 ______________________________________ Previous polarity Next DSV ______________________________________ + DSV - CDS - DSV + CDS ______________________________________
The table selector 8 receives as its inputs the polarity inversion data S5 from the polarity register 5 and the DSV data S7 from the DSV adder 7, determines which of the tables of (+) or (-) to be selected based on these data, and outputs the table switching signals to the selectors 2c, 3c, and 4c. At this time, the relationship of the polarity inversion data S5 and DSV data S7 with the tables to be selected next are shown in the following Table 2.
TABLE 2 ______________________________________ Previous state DSV Polarity Table to be selected next ______________________________________ + + Table (+) + - Tahle (-) - or 0 + Table (-) - or 0 - Table (+) ______________________________________
In Table 2, Table (+) indicates that the data table (+) 2a, polarity table (+) 3a, and the CDS table (+) 4a are to be selected. Further, Table (-) indicates that the data table (-) 2b, polarity table (-) 3b, and the CDS table (-) 4b are to be selected.
FIG. 2 is a view of the configuration of the table selector 8.
As shown in FIG. 2, the table selector 8 is constituted by discriminators 8a and 8b for discriminating whether DSV&lt;0 and DSV=0, respectively, an OR circuit 8c, and an exclusive logical OR circuit 8d.
Next, an explanation will be made of the processing of the 8/9 coding apparatus 1 shown in FIG. 1.
Step S1: First, when the sector start indication signal S10 indicates the head of the sector, the polarity register 5 and the DSV adder 7 initialize these values.
Step S2: Next, the table selector 8 outputs the table selecting signal S8 found under the conditions shown in above Table 2 and 4c by using the input polarity inversion data S5 and the DSV data S7 to the selectors 2c, 3c.
By this, in the data table 2, the polarity table 3, and the CDS table 4, either of the tables (+) or (-) are selected.
Step S3: Then, based on these selected tables, in the data table 2, the 9-bit NRZL data S2 is found from the 8-bit input data S0. This NRZL data S2 is converted to the 9-bit NRZI in the converter 6.
Step S4: Based on the selected CDS table, the CDS data S4 corresponding to the input data S0 is output from the CDS table 4 to the DSV adder 7.
Then, at the DSV adder 7, the 5-bit DSV data is generated based on Table 1 by using the polarity inversion data S5, the CDS data S4, and the sector start indication signal S10 and is output to the table selector 8.
Further, based on the selected polarity table, the polarity inversion data S3 corresponding to the input data S0 is output from the polarity table 3 to the polarity register 5. The value of the polarity register 5 is updated by this polarity inversion data S3.
Step S5: Returning to step S2 again, the processing for the next input data S0 is carried out.
Next, an explanation will be made of the conventional 8/9 coding apparatus 21 not having the CDS table.
FIG. 3 is a view of the configuration of the conventional 8/9 coding apparatus 21 not having the CDS table.
As shown in FIG. 3, the 8/9 coding apparatus 21 is not provided with the polarity table and the CDS table. Namely, in the CDS calculator 25, the 5-bit CDS data S25 is calculated based on the 9-bit NRZI format output data S21 output from the converter 26. Further, the converter 26 generates the polarity inversion data from the NRZL data S2, feeds back this polarity inversion data S26 again and, at the same time, outputs the same to the table selector 28. The DSV adder 27 generates the 5-bit DSV data based on the CDS data S25 and the sector start indication signal S10 and outputs this DSV data S27 to the table selector 28.
The table selector 28 generates the table selecting signal based on the DSV data S27 and the polarity inversion data S26 and outputs this table selecting signal S28 to the selector 2c of the data table 2.
According to the 8/9 coding apparatus 21, the configuration of the apparatus can be simplified since it is not provided with the polarity table and the CDS table.
In the above 8/9 coding apparatus 1, however, when the table selector 8 performs the selection of the tables under the conditions shown in Table 2, it is necessary to decide which of the conditions of A or B shown in the following (1) stand.
A: DSV is positive PA1 B: DSV is negative or zero
(1)
Note that DSV is usually expressed by using a binary value of the complement of 2 or an offset binary value.
However, when performing the above decision shown in (1) for the DSV data expressed by the binary value of the complement of 2 etc. in this way, the condition under which the bit of the DSV data changes and the condition under which the result of decision shown in above (1) changes do not coincide. For this reason, in the table selector 8, the decision of the conditions shown in the following (2) and (3) is carried out with the circuit configuration shown in FIG. 2, the results of these decisions are combined, and then the decision shown in above (1) is carried out. EQU DSV&lt;0 (2) EQU DSV=0 (3)
Namely, the table selector 8 performs the decisions as shown in the following (4) and (5) by using the results of the decisions of the conditions of the above (2) and (3).
______________________________________ When "(2) is false" and "(3) is false", A of the above (1) stands (4) When "(2) is true" or (3) is true", B of the above (1) stands (5) ______________________________________
However, since the table selector 8 has to carry out such a complex operation, there is a problem in that the circuit configuration becomes complex as shown in FIG. 2 and, at the same time, the processing time becomes long.
Further, in the above 8/9 coding apparatus 1, the DSV data S7 output from the DSV adder 7 becomes a value within a range of from -8 to +9 at the punctuation of the input data words when including the influence of the Sync pattern. For this reason, the DSV adder 7 is required to have a 5-bit addition, subtraction, initialization, and Sync part processing function.
Further, in the above 8/9 coding apparatus 1, the CDS data recorded in the CDS table 4 has a value within a range of from -6 to +8, therefore 5 bits become necessary to express the CDS data by a binary value.
A similar problem occurs also in the 8/9 coding apparatus 21 explained above referring to FIG. 3.